1. Field of the Invention
The present invention relates to a cache memory system. More particularly, the present invention relates to a cache system that can change a capacity (a memory size) of a cache memory.
2. Description of the Related Art
As a method of suppressing a power consumption of a cache system, there is a method of dividing a data memory and a tag memory into a plurality of parts and restricting access to addresses of some of the divided parts only to reduce a power consumption at the time of access. Further, in recent years, to counteract the problem of power usage at the time of no access, there is adopted a method of inhibiting access to some of the ways in a set-associative cache to reduce a capacity of the cache memory and turning off a power supply for a memory assigned to these ways. In this method, when access to a given way is inhibited, data stored in this way is invalidated, and hence the data must be written back in a memory in a lower layer. Contrarily, when canceling access inhibition, stored data does not have to be processed at all.
However, in the case of the method that inhibits access to some of the ways, the number of ways must be reduced to decrease a capacity of the cache memory, the method becomes weak in regard to conflict misses, resulting in a problem that performances as the cache memory are degraded. Furthermore, there is also a problem that the capacity cannot be increased/decreased beyond the number of ways.
It is to be noted that the following suggestion (Literature 1) is present as a technology concerning the present invention (see, for example, Jpn. Pat. Appln. KOKAI Publication no. 2007-172623).
Literature 1 relates to an operating method of an integrated circuit having a cache memory of a variable size, and a size of the cache memory is changed by using a mask that varies in accordance with a cache memory size signal. However, when changing a size of the cache memory, access to the cache memory must be inhibited.